`timescale 1ns / 1ns
module doors_tb;
 reg A;
 reg B;
 wire NotGate;
 wire AndGate;
 wire OrGate;
 wire NandGate;
 wire NorGate;
 wire XorGate;
 
 wire LedNotGate;
 wire LedAndGate;
 wire LedOrGate;
 wire LedNandGate;
 wire LedNorGate;
 wire LedXorGate;
 doors U(A, B, NotGate, AndGate, OrGate, NandGate, NorGate, XorGate,LedNotGate, LedAndGate, LedOrGate, LedNandGate,LedNorGate,LedXorGate);
initial begin
  A = 1'b0; B = 1'b0;    #100;
  A = 1'b0; B = 1'b1;    #100;
  A = 1'b1; B = 1'b0;    #100;
  A = 1'b1; B = 1'b1;    #100;
      $stop;
  end
endmodule